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Altera_Forum's avatar
Altera_Forum
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16 years ago

Problem with LPM_MUX

This is a basic problem but it is catching me out, I am trying to implement a simple 2-to-1 mux using the LPM but Quartus is kindly telling me I am using the 2D_std_logic type incorrectly 

mux            :    LPM_MUX
        GENERIC MAP(
                    LPM_WIDTH         =>    12,     
                    LPM_SIZE            =>    2,      
                    LPM_WIDTHS       =>    1
        )            
        PORT MAP (
                    DATA(0, 11 downto 0)  =>   Ramp_Up_I(11 downto 0),
                    DATA(1, 11 downto 0)  =>   Ramp_Down_Q(11 downto 0),                        SEL                           =>   clockdivide(0),                 
                    RESULT(11 downto 0)   =>   Muxed_IQ(11 downto 0)
        );
The error is

slice of object cannot be specified for object that has an array type of more than one dimension

Any help would be greatly appreciated

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    there is no such thing as a 2D_std_logic type. You also cannot index DATA like you have (it is illegal VHDL)

    Did you generate the mux via the megawizard? or are you trying to do it manually?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi Tricky, thanks for replying. I am trying to implement it manually. The std_logic_2d type is used by Altera in the LPM component declaration, this is taken directly from Altera

    component LPM_MUX 

            
generic (LPM_WIDTH        : natural;    -- MUST be greater than 0 
            LPM_SIZE           : natural;    -- MUST be greater than 0 
            LPM_WIDTHS      : natural;    -- MUST be greater than 0 
            LPM_PIPELINE     : natural := 0;
            LPM_TYPE          : string := L_MUX;
            LPM_HINT          : string := "UNUSED");
port (    DATA                : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
                 ACLR                 : in std_logic := '0';
                 CLOCK                 : in std_logic := '0';
                 CLKEN                 : in std_logic := '1';
                 SEL                 : in std_logic_vector(LPM_WIDTHS-1 downto 0); 
                 RESULT             : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I hate it when altera do odd things with std_logics

    basically, std_logic_2D is nothing to do with std_logic_vector, so you cannot assign std_logic_vectors directly to std_logic_2D types, other than doing it bit by bit. You have create a local std_logic_2D type signal and assign stuff into that.

    But what makes it more annoying is that you cannot use (N downto M) or (N to M) in 2D arrays. You can only access individual elements (in this case bits), or assign the entire thing.

    Now if only they'd made an array of std_logic_vectors, instead of a 2D array of std_logic, then everything would be fine!

    My advice - Dont use the LPM library for simple things - just imply it in the code: 

    
signal a, b : std_logic_vector(11 downto 0);
....
--for an uclocked mux:
result <= a when sel = '0' else b;
--for a clocked mux
process(clk, reset)
begin
  if reset = '1' then
    result <= (others => '0');
  elsif rising_edge(clk) then
    if sel = '0' then
      result <= a;
    else
      result <= b;
    end if;
  end if;
end process;