I hate it when altera do odd things with std_logics
basically, std_logic_2D is nothing to do with std_logic_vector, so you cannot assign std_logic_vectors directly to std_logic_2D types, other than doing it bit by bit. You have create a local std_logic_2D type signal and assign stuff into that.
But what makes it more annoying is that you cannot use (N downto M) or (N to M) in 2D arrays. You can only access individual elements (in this case bits), or assign the entire thing.
Now if only they'd made an array of std_logic_vectors, instead of a 2D array of std_logic, then everything would be fine!
My advice - Dont use the LPM library for simple things - just imply it in the code:
signal a, b : std_logic_vector(11 downto 0);
....
--for an uclocked mux:
result <= a when sel = '0' else b;
--for a clocked mux
process(clk, reset)
begin
if reset = '1' then
result <= (others => '0');
elsif rising_edge(clk) then
if sel = '0' then
result <= a;
else
result <= b;
end if;
end if;
end process;