New Contributor
Regular ContributorHi,
As I understand it, you seems to observe the din_ready from the Deinterlacer II de-asserts after feeding into video data in simulation. When din_ready is de-asserted, the IP is unable to receive further data.
To facilitate further debugging, would you mind to create a simple test design ie with TPG II -> DIL II (+ memory) -> CVO run with Modelsim simulation. YOu may start with small video resolution ie 100x100 to use on-chip memory to further isolate out the memory controller. Once the simple test design is simulating correctly, you may then slowly replace the component to test out. This would be helpful to narrow down to the root cause.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorThank you for the response. I followed your advice, but I get the same problem.
