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Altera_Forum
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12 years ago

Problem with asynchronous FSM - VHDL

I have a problem with implementation of finite state machine, which is responsible for detection of motor direction based on signals from HALL sensors. The system has three inputs (HALL1, HALL2, HALL...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

In my simulation(ModelSim) the output DIR_SIGNAL changes from 0 to 1 repeatedly. I used the three inputs set as clock patterns with periods 100,1000,2000