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Where is your testbench?
Have you also considered Kaz's comment that most FPGA designs are synchronous guys as that is how FPGAs are designed. You're unlikely to get Async help on this board.
Why have you not used a clock?
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The board, what I work with is self-built controller for BLDC motor, where Altera was prepared to do only combinational functions (CLK pins are not connected). I would like to implement additional feature in Altera without interference in hardware of this system - this is the reason, why I want to do this in asynchronous mode.
Results of simulation are below.
https://www.alteraforum.com/forum/attachment.php?attachmentid=8337 So, during first 30 ns DIR_SIGNAL is unsigned and this is correct. From 30 ns until 180 ns DIR_SIGNAL is 0 and this is also correct, because for clockwise direction this output should be 0. The problem is, that during changing direction of the motor (after 180 ns) the output DIR_SIGNAL doesn't change from 0 to 1 and I really don't understand why, because as you can see on 'count' output the transitions between states are good.
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