Problem with asynchronous FSM - VHDL

I would like to renew this topic. After some time, I decided to design an asynchronous state machine. Code is below:

library ieee ;
use ieee.std_logic_1164 .all;
use ieee.std_logic_signed .all;
 entity DIR_AUT is
 port ( H1_SL, H2_SL, H3_SL: in STD_LOGIC ;
 DIR_SIGNAL : out bit;
 count : out STD_LOGIC_VECTOR (2 downto 0));
 END DIR_AUT;
 architecture behavior of DIR_AUT is
     type state_type is (A, B, C, D, E, F);
     signal y_act : state_type; 
    signal hall: std_logic_vector (0 to 2); 
 begin
    hall <= H1_SL&H2_SL&H3_SL;
  process (hall, y_act) -- state table
   begin
    case hall is
        when "100" => 
          if (y_act = B) then DIR_SIGNAL <= '1'; y_act <= A;
          elsif (y_act = F) then DIR_SIGNAL <= '0'; y_act <= A;
          else y_act <= A;
          end if;
       when "101" =>  
          if (y_act = C) then DIR_SIGNAL <= '1'; y_act <= B;
          elsif (y_act = A) then DIR_SIGNAL <= '0'; y_act <= B;
          else y_act <= B;
          end if;
       when "001" => 
          if (y_act = D) then DIR_SIGNAL <= '1'; y_act <= C;
          elsif (y_act = B) then DIR_SIGNAL <= '0'; y_act <= C;
          else y_act <= C;
          end if;
       when "011" => 
          if (y_act = E) then DIR_SIGNAL <= '1'; y_act <= D;
          elsif (y_act = C) then DIR_SIGNAL <= '0'; y_act <= D;
          else y_act <= D;
          end if;
       when "010" =>
          if (y_act = F) then DIR_SIGNAL <= '1'; y_act <= E;
          elsif (y_act = D) then DIR_SIGNAL <= '0'; y_act <= E;
          else y_act <= E;
          end if;
       when "110" => 
          if (y_act = A) then DIR_SIGNAL <= '1'; y_act <= F;
          elsif (y_act = E) then DIR_SIGNAL <= '0'; y_act <= F;
          else y_act <= F;
          end if;
       when others => y_act <= A;
    end case ;            
     end process ; -- state_table
with y_act select
count <= "000" when A,
         "001" when B,
         "010" when C,
         "011" when D,
         "100" when E,
         "101" when F,
         "111" when others;
end behavior ;

I used additional count output as a help just see in every moment what is the actual state of FSM. So, transitions between states seems to be really well, bu the problem now is, taht the output DIR_SIGNAL doesn't change and during whole simulation is on the same level. I really can not find a mistake in above code. I would be really grateful, if you know where can be a problem.