Problem with asynchronous FSM - VHDL

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Thank you for your answer. So, if I good understand - without external clock signal I can not deal with this task?

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FPGA design is based on clk. However in some cases one can do without it (as did old digital engineers) provided you are really skilled in asynchronous design, I am not and so are most of fpga designers.

Is't that difficult to get clock signal? designing asynchronously will be more difficult than getting a clk on board. At the end it might be just possible if your design is simple and accepts delay variations.