Problem with asynchronous FSM - VHDL

your above logic will simply set q1 to 1 and q2 to 1 for ever once a clock edge arrives (assuming reset applied once).

What you need is a proper clock signal and not one gated from xoring HALL1/HALL2/HALL3.

your clock signal could be just fast enough to sample the HLL signals as below.

Without clock you cannot design safely.

Once yu have clock independent of HALL signals then you sample to detect rising/falling edge of your original square signal as follows:

process
begin
if rising_edge(clk) then
   sq_d <= square;
   if square = '1' and sq_d = '0' then  -- this is now clk enable
   --do whatever at this edge
   end if;
   if square = '0' and sq_d = '1' then -- another clk enable
   -- do whatever for falling edge
   end if;
end if;
end process;