Problem with asynchronous FSM - VHDL

I did as you wrote and created register - code is below

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY CLK_REG IS
port (clk, reset   : IN STD_LOGIC;
      q1, q2 : OUT STD_LOGIC );
END CLK_REG;
ARCHITECTURE arch9 OF CLK_REG IS
BEGIN
   -- Register with active-high clock
     PROCESS (clk, reset)                      
   BEGIN
       IF reset = '0' THEN            
          q1 <= '0';
       ELSIF clk'EVENT AND clk = '1' THEN
          q1 <= '1';
       END IF;
   END PROCESS;
   -- Register with active-low clock
     PROCESS (clk, reset)                      
   BEGIN
       IF reset = '1' THEN            
          q2 <= '0';
       ELSIF clk'EVENT AND clk = '0' THEN
          q2 <= '1';
       END IF;
   END PROCESS;
END arch9;

I enabled this by clock created from hall signals and expected to get on my outputs: q1 = 1, and q2 = 0 when clock = 1; q1 = 0, and q2 = 1 when clock = 0;

And this part works. Then I changed a synchronous part of my state machine as below:

 process (q1, q2)
 begin
 if (q1 = '0' and q2 = '0') then
      y_act <= A;
 elsif (q2 = '1' and q1 = '0' ) then
      y_act <= y_next;
 elsif (q1 = '1' and q2 = '0') then
      y_act <= y_next;
 end if;
 end process ;

Unfortunatelly this part doesn't work at all. It changes all the time states only between A and B. Can you tell what mistake I do in this case?