Forum Discussion
Altera_Forum
Honored Contributor
16 years agoAre you simulating this or actually running it in a part? I'm not sure you are generating the logic you expect. There is a massive amount of combinatorial logic created here.
Here is what things will be every time datawrite goes high: arr[address] will be datain a1 will be datain a2 will be datain temp1 will be datain (Is this what you wanted?) temp2 will be datain * datain (Is this what you wanted?) temp3 will be (datain * datain) / datain (Is this what you wanted? Should be equivalent to datain) arr_[address] will be (datain*datain) / datain (Is this what you wanted?) Is it possible that you are abusing the Verilog blocking "=" operator and should instead be using the non-blocking operator "<="? Jake