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Altera_Forum's avatar
Altera_Forum
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12 years ago

problem with an addition in a vhdl code

Hello, I have written the following code but I do not take the right results from the addition: met <=met+monada; I think that the problem is that I have the signal met twice. Specifically...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Thank you for your helpful information.

I do not write: met <= met + 25 because I want to increase the variable 'met' step by step.

Specifically I want 'met' to take the values 1 then 2 then 3 and etc and this is the reason that I use the the loop in my code.

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I think you should use "vector" signals instead of sign or unsign. Also you were designing circuit using HDL code insdead of writing c code! So you should make a clock involve in your hardware codes, and design synchronized circuit.