problem with an addition in a vhdl code

From this code - I guess you have a software background?

There is a major problem with the code in that the process is sensitive to a signal that is updated inside itself - so this process will just run in an infinite loop in simulation and you'll probably hit the iteration limit.

Initialisation is that - the value given to a signal/variable when the simulation is started. In your code, it has no initialisation value, so as the signed type is an array of std_logic it will initialise to "UUUUUU" (uninitialised) as per the type definition (uninitialised values take the leftmost value).

If you want to increase this value by 25, why not simply write:

met <= met + 25?

I suggest you go back to a VHDL tutorial, preferably one that talks about digital logic too. If your digital logic knowledge is lacking - I suggest you read up on that to. When you're more confident, draw your circuit out on paper. HDL stands for hardware description language, so if you dont know what the circuit should be, how do you expect to describe it?