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JTUCK3's avatar
JTUCK3
Icon for New Contributor rankNew Contributor
7 years ago

Problem simulating Verilog ip catalog uart with my VHDL design using Modelsim Altera starter edition

The IP catalog seems to generate Verilog, even though I ask for VHDL. It appears to create a top level VHDL wrapper for its Verilog design. As I'm using VHDL for my design, I get a simulation error "...
Tricky's avatar
Tricky
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

What version are you using? Modelsim starter has supported mixed language for a few versions.

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Also​, a lot of IP is developed only in sv now, and developing dual language versions is not happening, a vhdl wrapper is the best you're likely to get. Xilinx won't even provide the wrappers in. Vhdl now.