Forum Discussion
JTUCK3
New Contributor
New ContributorProblem simulating Verilog ip catalog uart with my VHDL design using Modelsim Altera starter edition
The IP catalog seems to generate Verilog, even though I ask for VHDL. It appears to create a top level VHDL wrapper for its Verilog design. As I'm using VHDL for my design, I get a simulation error "...
Tricky
Occasional Contributor
Occasional ContributorWhat version are you using? Modelsim starter has supported mixed language for a few versions.
Also, a lot of IP is developed only in sv now, and developing dual language versions is not happening, a vhdl wrapper is the best you're likely to get. Xilinx won't even provide the wrappers in. Vhdl now.
