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JTUCK3's avatar
JTUCK3
Icon for New Contributor rankNew Contributor
7 years ago

Problem simulating Verilog ip catalog uart with my VHDL design using Modelsim Altera starter edition

The IP catalog seems to generate Verilog, even though I ask for VHDL. It appears to create a top level VHDL wrapper for its Verilog design. As I'm using VHDL for my design, I get a simulation error "...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

My guesses are that the ModelSim starter edition does not allow Mixed language simulation, ie, VHDL and Verilog mixed designs. You may need to get the subscription version for mixed language simulations.

Try generating the IP again and if the issue persists, i suggest contacting Intel support directly.