Problem simulating FSM

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why not post the origional code?

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Sure, by the way, all my FSM projects have the same issue, so I'll post a simple example because

that one is very long.

module FSM(clock, reset, w, z);
	input clock, reset, w;
	output z;
	
	reg  y_Q, Y_D;	// y_Q represents the current state, Y_D represents the next state.
	parameter A = 4'b0000, B = 4'b0001, C = 4'b0010, D = 4'b0011, E = 4'b0100,
	F = 4'b0101, G = 4'b0110, H = 4'b0111, I = 4'b1000;
	
	always@(w, y_Q)
	begin: state_table
		case(y_Q)
			A: if(!w) Y_D = B;
				else Y_D = F;
			B: if(!w) Y_D = C;
				else Y_D = F;
			C: if(!w) Y_D = D;
				else Y_D = F;
			D: if(!w) Y_D = E;
				else Y_D = F;
			E: if(!w) Y_D = E;
				else Y_D = F;
			F: if(!w) Y_D = B;
				else Y_D = G;
			G: if(!w) Y_D = B;
				else Y_D = H;
			H: if(!w) Y_D = B;
				else Y_D = I;
			I: if(!w) Y_D = B;
				else Y_D = I;
			default: Y_D = 4'bxxxx;
		endcase
	end	// state_table
	
	always @(posedge clock)
	begin: state_FFs
		if(~reset) y_Q <= A;
		else y_Q <= Y_D;
	end // state_FFs
	
	// ---------------------------
	// Outputs
	// ---------------------------
	assign z = (y_Q == E) | (y_Q == I);
endmodule

Thank you so much sir, your help is so appreciated.