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Hi sstrell,
I fixed this problem. It is not because of timing requirement, it is because I use the same clock input(CLK, shown in my code before) for this two ADCs. Actually these two ADCs can not work at the exactly same time. so they can not share the same clock.
I will set DOUT as a basic clock to decrease that warning! DOUT is a combined pin, if there is no new data from ADC, DOUT acts as ready signal. Once there are new datas from ADC, DOUT trigger my board to send in SCLK and read data out.
Thank you very much for your advise.
Yours
Yonghang Tian
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Hi, yonghang,
Congratulations on you make it! And I meet the same problems, I configured the same three ADCs module in my project, see in the following,
sample sample_adc1(
.clk(clk),
.rst_n(rst_n),
.miso(miso1),
.mosi(mosi1),
.csn(csn1),
.sclk(sclk1),
.data(data1)
);
sample sample_adc2(
.clk(clk),
.rst_n(rst_n),
.miso(miso2),
.mosi(mosi2),
.csn(csn2),
.sclk(sclk2),
.data(data2)
);
sample sample_adc3(
.clk(clk),
.rst_n(rst_n),
.miso(miso3),
.mosi(mosi3),
.csn(csn3),
.sclk(sclk3),
.data(data3)
);
//clk--input external clock 25MHZ,
rst_n--reset
miso--AD7888 output sample data to FPGA
mosi--FPGA output configure data to AD7888
csn--chip select
sclk--FPGA output serial clk to AD7888
my problem is : when I only use one ADC in my project , the result is correct , but when I use two or three ADCs module , There is interference between the data (I use in system sources and probes editor to watch the result),
thus i can't get all correct data and get warning messages:
Warning (332060): Node: sample:sample_adc3|csn was determined to be a clock but was found without an associated clock assignment.
...........................................(much)
I changed the clk , using three output clock form PLL module, but i seems no difference, I need your help! THANKS!
Honored Contributor
