Problem in simulation o/p of circular buffer

You dont say if the problem is in simulation or on FPGA.

I can see a massive problem with the first process - you have r_data assigned outside of a clock, plus it is also assigned from a variable. You cannot have output assigned like this in a process. You'll need to take it out from the process and put array_reg back as a signal like you had before.

Ive simulated it and it seems to work fine - I get output. Whats the problem you're getting?