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SHuan29's avatar
SHuan29
Icon for New Contributor rankNew Contributor
7 years ago

Problem in simulating Arria10 PLL IP with Cadence NCsim

I had been simulating with ArriaV IPs successfully. Recently I start to use Arria10 device. I tried to simulate the new FPGA in the same way I run ArriaV simulation. However I got the following error...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Have you compiled the FPGA / CPLD device libraries for CAdence NC Sim? If not, you have to do that first from Quartus II via the Tools -> FPGA library compiler. Select the appropriate simulator, key in the path to the executable and then select the devices to compile. After this you can simulate your design using the chosen simulator.