Problem in building a LCD panel controller in SOPC

I use the quartus II 9.0,

I want to creat a TFT controller , but got some problem:

TFT panel : 800*480 、24bit parallel RGB（three colors in parallel）data out;

question 1:

in video sync generator

Data stream bit width:24

Beats per pixel:1

in pixel converter (bgr0-> bgr)

Source symbols per beat:3

error:

the source has 8 bits per symbol while the sink has 24;

the source has 3 symbols per beat while the sink has 1;

I feel puzzled with this,

In 24bit parallel RGB, what parameters should set in above two blocks?

or Video sync generator can’t generate 24bit parallel RGB signals?

question 2:

I use a 8bit data width sdram,but set the the data width of SGDMS to 64bit? is that proper?

question 3:

I download nios_lcd_3c120 design example from Altera,but it didn’t use frame buffer block of video and image processing, does frame buffer block is a new block of quartus II 9.0? is it necessary to use this block to build buffer in external memory ? (nios_lcd_3c120 doesn’tuse)

And how to use it?