Problem about building LCD display with SOPC using DE0-nano

To ensure your memory interface is working properly I recommend creating a system with the following:

Nios II core

JTAG debug module

Biggest Onchip memory you can fit into the FPGA to serve up code

JTAG UART

SDRAM controller

Assuming you have enough onchip memory then you can use the mem_test_small application template in the Nios II EDS. Using a CPU is not a good stresstest but it can find address/data shorts sufficiently. If you don't have enough memory you can probably study that application and figure out ways to reduce the code footprint to the point where you can fit it into onchip memory.

My motto is "until you have tested your external memory, it doesn't work!". Just like Dave said, debug using small designs so that you can pinpoint the problem easier.