problem (?) using shared variables

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you shouldnt use clk_en to generate a clock. Forget about generating a 2nd clock. Just use the clk_en directly.

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Hi,

Based on your recommendation, I developed the following code:

library ieee;
use ieee.std_logic_1164.all;
entity clock_gen is
   generic(N: integer := 10);
   port(
      mclk:  in std_logic;
      rst:  in std_logic;
      clk: out std_logic);
end clock_gen;
architecture arch of clock_gen is
   signal cnt: integer := 0;
begin
   process(mclk, rst)
   begin
      if(rst = '1') then
         cnt <= 0;
	 clk <= '0';
      elsif(rising_edge(mclk)) then
         cnt <= cnt + 1;
	 if(cnt = N) then -- this will give you an enable rate of clk/N
            clk <= '1';
         else
            clk <= '0';
         end if;
      end if;
   end process;
end arch;

The simulation of this code produced the following result:

https://www.alteraforum.com/forum/attachment.php?attachmentid=7549

A "return to zero" was needed. Also, I would prefer a 50% duty cycle clock generator. So I did some modifications on your recommendation and produced the following code:

library ieee;
use ieee.std_logic_1164.all;
entity clock_gen is
   generic(N: integer := 20);
   port(
	   mclk:  in std_logic;
           rst:  in std_logic;
	   clk: out std_logic);
end clock_gen;
architecture arch of clock_gen is
   signal    cnt: integer := 0;
begin
   process(mclk, rst)
   begin
      if(rst = '1') then
         cnt <= 0;
	 clk <= '0';
      elsif(rising_edge(mclk)) then
         cnt <= cnt + 1;
	 if(cnt >= (N - 1)/2) then -- this will give you an enable rate of clk/N
            if(cnt = (N - 1)) then
               clk <= '0';
	       cnt <= 0;
	    else
	       clk <= '1';
	    end if;
         else
            clk <= '0';
         end if;
      end if;
   end process;
end arch;

Regards

Jaraqui