Honored Contributor
Honored ContributorI am testing with others target device/EDA tool.
In this week, not sure, I will have at hands a DE0, and I will try with it too. The reset on DE0 is '0' sensitive (not '1', as the rst presented in this version). The internal oscillator has the same frequency (50 MHz). Here is the version with numeric...
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------
entity counter_with_sharedvar is
port (mclk: in std_logic;
rst: in std_logic;
digit1, digit2: out std_logic_vector(3 downto 0));
end entity;
------------------------------------------------------
architecture counter of counter_with_sharedvar is
shared variable temp1, temp2: integer range 0 to 9;
signal clk: std_logic;
begin
----------------------------------
proc0: process(mclk, rst)
variable count: integer := 0;
begin
if(rst = '1') then
count := 0;
elsif(mclk'event and mclk='1') then
if(count < 25_000_000) then
clk <= '0';
count := count + 1;
elsif(count >= 25_000_000) then
if(count = 50_000_000) then
count := 0;
clk <= '0';
else
count := count + 1;
clk <= '1';
end if;
end if;
end if;
end process proc0;
----------------------------------
proc1: process (clk, rst)
begin
if(rst = '1') then
temp1 := 0;
elsif (clk'EVENT and clk='1') then
if (temp1=9) then
temp1 := 0;
else
temp1 := temp1 + 1;
end if;
end if;
end process proc1;
----------------------------------
proc2: process (clk, rst)
begin
if(rst = '1') then
temp2 := 0;
elsif (clk'EVENT and clk='1') then
if (temp1=9) then
if (temp2=9) then
temp2 := 0;
else
temp2 := temp2 + 1;
end if;
end if;
end if;
end process proc2;
----------------------------------
digit1 <= std_logic_vector(to_unsigned(temp1, 4));
digit2 <= std_logic_vector(to_unsigned(temp2, 4));
end architecture;
