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Altera_Forum's avatar
Altera_Forum
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15 years ago

presettable and clearable registers warning in Quartus, how to fixed it?

hi,

When i check my syntheis report in Quartus, there is some latch warnings

"

Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.

Warning (13310): Register "vga_controler_line:vga_cntl_1|hsync_out" is converted into an equivalent circuit using register "vga_controler_line:vga_cntl_1|hsync_out~_emulated" and latch "vga_controler_line:vga_cntl_1|hsync_out~latch"

"

my code is just like this

"

always @(posedge clk or posedge rst)

if(rst)

hsync_out <= ~SYNC_POLARITY; //SYNC_POLARITY is register setting

else

hsync_out <= xxx;

"

How i can code the better way to void Qurartus synthesis latch warning?

Thanks very much,

14 Replies

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  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    In the present code, the priority is for end_rd_or_wr according to sequential code evaluation (the last assignment wins). You have to exchange both lines or use an if ... else ... construct to set it different.

    As an additional remark, asynchronous ALE latch operation is usually chosen on purpose. Analyze the bus timing to check if synchronous ALE can work as well.

    --- Quote End ---

    The 2 signals would never occur at the same time, so its a don't care.

    Can you elaborate on what you are suggesting for asynchronous ALE? The ale signal is in fact asserted well after the address is put on the bus and for several clk cycles.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hello,

    The below code is giving me the following warnings: 

    Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
Warning: Timing Analysis is analyzing one or more combinational loops as latches

    It sounds maybe a little paranoid but I always want to have my code warning-free.

    Coud someone maybe explain to me how to fix these warnings.

    Thank you for the responses,

    Wamor 

     
 process(clk, reset_n, delay_out_reg, count_out_reg) 
 begin
  if reset_n = '0' then
   multi_IO_output_counter <= delay_out_reg;
   multi_IO_pulse_counter <= count_out_reg;
  else
   if rising_edge(clk) then
    if multi_IO_clock_enable = '1' then
     if multi_IO_output_counter > clock_divide_out_reg - 1 then
      multi_IO_output_counter <= (others => '0');
      if multi_IO_pulse_counter > 0 then
       multi_IO_pulse_counter <= multi_IO_pulse_counter - 1;
      end if;
     else
      multi_IO_output_counter <= multi_IO_output_counter + 1;
     end if;
    else
     multi_IO_output_counter <= delay_out_reg;
     multi_IO_pulse_counter <= count_out_reg;     
    end if;
   else
    -- need to do something here??
   end if;
  end if;
 end process;
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Your are assigning at reset to "multi_IO_output_counter" ...etc another signal.

    When you do that it implies that the clocked register "multi_IO_output_counter" has also to acquire a value from external logic on its q output outside clocked edge. The compiler then builds some unclocked logic on q output that latches the async value until clock edge arrives.

    normally we assign a constant here at reset release.Here the flip can inherently apply zero. It can also apply 1 and you get a warning that can be ignored.

    If you do want that then apply reset synchronously.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thank you Kaz for your quick response.

    With your help I fixed the warnings.

    Regards,

    Wamor