Preserve root partition in a debugging scenario

Hi Romain,

I will answer your question accordingly.

Is it absolutely necessary to define a logic lock region for the core partition?

Answer: Yes, this is the flow to use if you want to preserve the root partition.

If yes, is it absolutely necessary to set the "Size/State" parameter to "Fixed/Locked"? Ideally, I would like to let Quartus do the fit itself the first time, and then reuse the selected location on a chip.

Answer: I believe that you want to use float. Did you get any error if you set to float? Can you post out the error message here? Most probably is because, if you set the float, the sized of the core to be locked is unknown, it would be hard for the Quartus to determined how large your core logic. The reason is for periphery, they need to know where does your core logic resides so that the routing is not long when connected to the core logic from the pheriphery.

If yes, what are exactly the limitations concerning the "origin" parameter in the logic lock regions? I tried to retrieve a location used in the already compiled design for that block, found through chip planner, and set X108_Y118 as origin (device is 10AX066H2F34E1HG) but Quartus tells me that this location is "not a legal origin for a logic lock region".

Answer: Can you provide me the screenshot of your chip planner? Usually, you can locate this block for the location X108_Y118. Look whether it is LAB/DSP/RAM block. Also, can you post the full error message here? There should be reason why it mention it is not a legal origin. Or you can provide us the design.qar files to look into it.

Finally, am I using the right method or is another method more suited to my objective?

Answer: If you are using A10, this will be the method. There are few methodologies that you can use:

intel.com/content/www/us/en/programmable/documentation/yrh1513988099640.html#nrw1536172493314 1.3 sections

If you are using S10, they are rapid recompile that you can used: https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/features/rapid-recompile.html

But A10 not supported.