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I ran into the exact same issue a while back and after a lot of effort gave up on the ivdep approach, and I was using 17.0. Having done it myself, you sometimes can refactor your code to get around the indirect address problem but in practice it's not always possible to do so without incurring other inefficiencies that make it not worth it (e.g. excess logic, which can waste a lot of resources, and not just FFs and LUTs, but even DSPs and BRAMs) .
What's strange is you can do what you're attempting to do in VHDL/Verilog without a problem. In my opinion Altera/Intel should add some sort of pragma to allow you to accept or specify address collision behavior (i.e. don't care about collisions, or rd before write, etc.).
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Thanks for your reply!
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