PowerPlay Power Analyzer for Clockless(Asynchronous) logic deigns

Basically, PowerPlay uses .sdc file clock information for Power Calculation especially for clock nodes.

http://www.altera.com/literature/hb/qts/qts_qii53013.pdf page 8-15

I found this information form the Knowledge centre.

http://www.altera.com/support/kdb/solutions/rd10102006_494.html

We have to use "transitions / s" instead of "%" for clockless or no timing constraints logic designs.

For more accurate power analysis, we are using .vcd file(Simulation based flow, Activity data) but we still need .sdc file for power analysis therefore I could not find any solution for clockless design using .vcd file from my testing.

Does anyone have ideas for this approach?

Can we still do the power analysis with .vcd file for non-constraints design(without .sdc file) or Clockless(Asynchronous) designs or Combinational logic only designs?

Does Altera PowerPlay support Asynchronous Logic Design power analysis?

Please let me know if I have some misunderstandings.