Honored Contributor
Honored Contributorpower estimation can be done in various stages but the easiest one is to compile,fit and then run powerplay.
Since your design is just few signals you can enter overall toggle rate.below is an example from altera: --- Quote Start --- The toggle percentage rangesfrom 0 to 100%. Typically, the toggle percentage is 12.5%, which is the toggle percentage of a16-bit counter. To ensure you do not underestimate the toggle percentage, you can use a highertoggle percentage. Most logic only toggles infrequently, and hence toggle rates of less than 50%are more realistic.For example, a T-flip-flop (TFF) with its input tied to VCC has a toggle rate of 100% because itsoutput is changing logic states on every clock cycle (Figure 3–2). Figure 3–3 shows an example ofa 4-bit counter. The first TFF with the LSB output cout0 has a toggle rate of 100% because thesignal toggles on every clock cycle. The toggle rate for the second TFF with output cout1 is 50%since the signal only toggles on every two clock cycles. Consequently, the toggle rate for the thirdTFF with output cout2 and fourth TFF with output cout3 are 25% and 12.5%, respectively.Therefore, the average toggle percentage for this 4-bit counter is (100 + 50 + 25 + 12.5) /4 --- Quote End --- you can enter toggle rate in powerplay r I think yu can also enter in quartus project settings Hence testbench is not applicable as quartus does not support that. I am not sure why you mentioned system clock but are not telling what is't for. normally we use clock in fpga design to clock registers and that is clock domain
