Forum Discussion

New Contributor

5 years ago

POWER_UP_LEVEL for Partial Reconfiguration

Hi. I use dcfifo ip core which has POWER_UP_LEVEL assisment for some registers. Quartus shows warnings: Critical Warning(19519): The instance assignment "POWER_UP_LEVEL" on register "...|rx_fifo...

sstrell

Super Contributor

5 years ago

The built-in help says to simply remove the assignments:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/wqhd_power_up_level_assignment_used_in_pr_partition.htm

Are you saying the IP added these assignments when you added it to your design? It seems like you can safely ignore this unless you have requirements for these registers after you perform a PR.

DNLDNL
New Contributor
5 years ago
This registers are part of FIFO Intel® FPGA IP(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fifo.pdf)

Therefore I can't remove the assignments.

Forum Discussion

POWER_UP_LEVEL for Partial Reconfiguration

Recent Discussions

Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP

Invalid license key (inconsistent authentication code)

Regarding the issue of UFM not starting

ram retiming

Reset Release IP for Agilex needs Stratix 10 device files installed!