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NilsLiang_WNC's avatar
NilsLiang_WNC
Icon for New Contributor rankNew Contributor
3 years ago

Postive edge detector design

I've met a unexpected behaviour with my design and I just can't figure it out why. First, I did some logic to detect the postive edge of input signal. Then I use the pulse to drive output signal to...
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago

Hello,

we would save many follow-up questions if you had revealed the test design from the start.

After Signal Tap sample clock is specified and we know that you registered signal_in, how about the source of reset? Are we sure that Signal Tap clock is continuously running before, during and after reset?

Do you get any compiler warnings about ignored register reset levels?

Regards

Frank