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I understand that the old simulation environment was easier for teaching purposes. You start with something 'simple' and don't need to explain test bench during the first lesson.
Unfortunately simple in this case can also mean unsafe.
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Only a testbench where the output of the simulation is also checked by the testbench's VHDL code could be called safe. The other case, where the designer 'visually' checks the result of the testbench simulation, is not any safer than the waveform stimulated one. I guess that most testbenches fall in the unsafe category (the checking ones are a lot of work ...), why not make life easy by using a wave editor to create the stimuli and peruse the results?
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Using a proper simulation environment prevents from taking bad designing habits that are difficult to remove.
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One could rather say that there are no 'bad' design habits, just 'less' or 'more' efficient ones.
Honored Contributor
