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Hi,
The other thing I've seen software people have trouble with is the inherently parallel nature of VHDL synchronous design. For example, in the VHDL code:
if rising_edge (clock) then
a <= a + 1;
if (a = 23) then
a <= 0;
end if;
end if;
it doesn't matter if the line that increments "a" is before or after the if statement. Everything happens at the same instant on the rising edge of clock based on the value of "a" calculated at the previous rising edge of clock.
Mark.
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Are you sure? The order of statements makes a difference here within a sequential process. Inserting increment statement after if condition means if condition is overwritten and will be ignored.
Honored Contributor
