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Altera_Forum's avatar
Altera_Forum
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8 years ago

PLL Simulation not working fine

Hello, I am using Quartus Prime 17.0 version. In that when I am using PLL IP for clock generation, then during simulation I am not getting continuous clock at the output rather getting continous c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hello,

Thanks for the answer but locked signal is working fine. Its like I am getting the required frequency at the output, but the clock generated, is not continuous. And yes there is requirement to use PLL.