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JLee25's avatar
JLee25
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4 years ago

PLL Reconfiguration Timing Constraint

Hi, I have a question on the PLL timing constraint when working with Cyclone V Pll reconfiguration. In my case, I have the PLL output 2 different frequency, 1 is 10MHz and the other is 300MH...
Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

regards,
Farabi