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Altera_Forum's avatar
Altera_Forum
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15 years ago

PLL issue

Hi I am using cyclone II and quartus II v6.0. In my design I have selected base clock 100MHz and want to select SOPC Builder clock with the help of PLL 130MHz and 4MHz(required for black and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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you'll probably prefer a 4 MHz clock enable rather than a divided clock.

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I am not getting you at this point, please will you explain?