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Altera_Forum's avatar
Altera_Forum
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15 years ago

PLL issue

Hi I am using cyclone II and quartus II v6.0. In my design I have selected base clock 100MHz and want to select SOPC Builder clock with the help of PLL 130MHz and 4MHz(required for black and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The factors displayed in the GUI are not the real factors, considering the feasible VCO frequency range. If you consult the Cyclone II device´handbook, you'll realize, that 4 MHz output can't be achieved. Cylone II also doesn't support cascading of PLL dividers, so you have to use a clock divider in the application logic. Depending on the intended operation of the 4 MHz domain, you'll probably prefer a 4 MHz clock enable rather than a divided clock.