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Altera_Forum
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18 years ago

PLL is not consistently producing a clock

QII 7.2sp1: I am using a Microtronix FireflyII board (CycloneII) and nios reference design. The design uses one pll to generate a 90mhz sdram clock from an on-board 24mhz osc, and another pll to g...
Altera_Forum's avatar
Altera_Forum
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18 years ago

So really the circuit is clock input pin -> PLL -> output pin. You know you're driving the input pin, but the output pin is stuck. That has nothing to do with timing constraints or some of the other stuff I mentioned, as it's basic connections. Double check the IO locations in the .fit.rpt, maybe look at the Chip Editor(you probably don't need to). The other possibilities I can think of:

- Do other things toggle? Maybe the part hasn't come out of configuration but the first thing you're looking at is this clock?

- Does the PLL have a reset you drive with logic? Maybe that's getting driven in some instances?

- Can you bring the clock out other pins or something like that?

Good luck, as there will probably be some debug required.