pll input ports as unconstrained input ports with TimeQuest

Another try:

I started a new project, added one pll with input 'clk' and c0 output and one sopc module with cpu, epcs_controller and sys_id.

The following sdc lines worked without any unconstrained i/o reports for the 'clk' port:

# #########################################

create_clock -period 37.037 -name my_clk -add [get_ports {clk}]

derive_pll_clocks

# #########################################

Then I changed the pll configurations and added c2. I connected this output to an output port/pin of the FPGA and called the port SCLK.

The same sdc file showed the unconstrained input port message for 'clk' again (like in the bigger project mentioned in the beginning of this thread)!

Question: Is it not possible to directly connect the pll output c2 to a FPGA pin??? If it is possible, how do I constrain the path from pll input, through pll output to FPGA output?

What jakobjones mentioned, caused the same report result:

# #########################################

create_clock -period 37.037 -name my_clk -add [get_ports {clk}]

create_generated_clock -name sys_clk -source [get_ports {clk}] -multiply_by 4 [get_nets {inst2|altpll_component|_clk0}]

create_generated_clock -name sdram_clk -source [get_ports {clk}] -multiply_by 4 [get_nets {inst2|altpll_component|_clk2}]

# #########################################

Also the following lines didn't work,

# #########################################

create_clock -period 37.037 -name my_clk -add [get_ports {clk}]

create_generated_clock -name sys_clk -source [get_ports {clk}] -multiply_by 4 [get_nets {inst2|altpll_component|_clk0}]

create_generated_clock -name sdram_clk -source [get_ports {clk}] -phase -144 [get_ports {SCLK}]

# #########################################

although the clock path from pll input (clk) to FPGA port (SCLK) is mentioned.

What's wrong with that?