pll input ports as unconstrained input ports with TimeQuest

Ok, new try without offset (for delay on PCB) and without derive_pll_clocks:

# #########################################

# clocks

create_clock -name {clk1} -period 37.037 [get_ports {clk1}]

create_clock -name {clk4} -period 37.037 [get_ports {clk4}]

create_clock -name {clk8} -period 37.037 [get_ports {clk8}]

# not needed right now

# create_clock -name {clk12} -period 37.037 [get_ports {clk12}]

# create_generated_clock -name {clk12_c0} -source [get_ports {clk12}] -multiply_by 4 [get_pins {inst4|altpll_component|pll|clk[0]}]

create_generated_clock -name clk1_c2 -source [get_ports {clk1}] [get_pins {inst2|altpll_component|pll|clk[2]}]

create_generated_clock -name clk4_c0 -source [get_ports {clk4}] [get_pins {inst3|altpll_component|pll|clk[0]}]

create_generated_clock -name clk4_c2 -source [get_ports {clk4}] -phase 90.00 [get_pins {inst3|altpll_component|pll|clk[2]}]

create_generated_clock -name clk8_c0 -source [get_ports {clk4}] -multiply_by 4 [get_pins {inst4|altpll_component|pll|clk[0]}]

create_generated_clock -name clk8_c2 -source [get_ports {clk4}] -multiply_by 4 -phase -144.00 [get_pins {inst4|altpll_component|pll|clk[2]}]

# #########################################

# slow asynchronous I/Os

# reset

set_false_path -from [get_ports {GDCRST}]

...

# #########################################

# sdram ports

set_input_delay -clock clk8_c2 -max 6.6 [get_ports {DQ[*]}]

set_input_delay -clock clk8_c2 -min 3.4 [get_ports {DQ[*]}]

set_output_delay -clock clk8_c2 -max 2.6 [get_ports {/CAS /RAS /WE /CS A[*] BA* CKE DQM* DQ*}]

set_output_delay -clock clk8_c2 -min -0.6 [get_ports {/CAS /RAS /WE /CS A[*] BA* CKE DQM* DQ*}]

# #########################################

Is this how you meant it?

Clocks summary:

clk1 -Base

clk1_c2 - Generated

clk4 -Base

clk4_c0 - Generated

clk4_c2 - Generated

clk8 -Base

clk8_c0 - Generated

clk8_c2 - Generated

report_sdc -ignored -panel_name "Ignored Constraints"

Info: No ignored assignments to report

But still:

Illegal Clocks 0

Unconstrained Clocks 0

Unconstrained Input Ports 3

Unconstrained Input Port Paths 4

Unconstrained Output Ports 0

Unconstrained Output Port Paths 0

Unconstrained Input Ports:

clk8 Unclocked

clk4 Unclocked

clk1 Unclocked

Unconstrained Input Port Paths

clk8 SCLK

clk4 PIXCLKI

clk4 PIXCLKI_n

clk1 CLK_VGA

And it doesn't matter, whether or not I add something like

# #########################################

create_generated_clock -name sdram_clk_pin -source [get_pins {inst4|altpll_component|pll|clk[2]}] -offset 0.5 [get_ports {SCLK}]

create_generated_clock -name pix_clk_pin -source [get_pins {inst3|altpll_component|pll|clk[2]}] -phase 90.00 -offset 0.5 [get_ports {PIXCLKI}]

create_generated_clock -name pix_clk_pin_n -source [get_pins {inst3|altpll_component|pll|clk[2]}] -phase 90.00 -offset 0.5 [get_ports {PIXCLKI_n}]

create_generated_clock -name clk_vga_pin -source [get_pins {inst2|altpll_component|pll|clk[2]}] -offset 0.5 [get_ports {CLK_VGA}]

# #########################################

after that first 'create_generated_clock' block, to have something driving the SCLK, PIXCLKI etc. pll c2 outputs.

What's wrong here?