pll input ports as unconstrained input ports with TimeQuest

You should run the "Report Ignored Constraints" report in TimeQuest.

Here is what I would do:

# clocks

create_clock -name {clk1} -period 37.037 [get_ports {clk1}]

create_clock -name {clk4} -period 37.037 [get_ports {clk4}]

create_clock -name {clk8} -period 37.037 [get_ports {clk8}]

create_clock -name {clk12} -period 37.037 [get_ports {clk12}]

# And here is what you do for generated clocks (except I don't know your design heirarchy so I'm guessing here)

create_generated_clock -name {clk12_c0} -source [get_ports {clk12}] -multiply_by 4 [get_pins {inst4|altpll_component|pll|clk[0]}]

create_generated_clock -name {sdram_clk} -source [get_ports {clk12}] -multiply_by 4 -phase -144.00 [get_pins {inst4|altpll_component|pll|clk[2]}]

Jake