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Altera_Forum
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16 years ago

pll input ports as unconstrained input ports with TimeQuest

The system contains a Cyclone II FPGA, SDR SDRAM and some other components. There is one crystal oscillator connected to the four dedicated pll input FPGA pins. The configuration includes 4 plls (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

That's the strangest part, all clocks seem to be there!

clk1 - Base (I created 4 clks for the 4 plls now, like suggested)

clk4 - Base

clk8 - Base

clk12 - Base

inst2|altpll_component|pll|clk[2] - Generated

inst3|altpll_component|pll|clk[0] - Generated

inst3|altpll_component|pll|clk[2] - Generated

inst4|altpll_component|pll|clk[0] - Generated

inst4|altpll_component|pll|clk[2] - Generated

sdram_clk_pin - Generated

virt_jtag_clk - Base

And there are no illegal or unconstrained clocks reported.