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Altera_Forum's avatar
Altera_Forum
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16 years ago

pll input ports as unconstrained input ports with TimeQuest

The system contains a Cyclone II FPGA, SDR SDRAM and some other components. There is one crystal oscillator connected to the four dedicated pll input FPGA pins. The configuration includes 4 plls (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It looks fine...

I think you get a warning if you don't set any input_delay on a clock input, but it shouldn't prevent the clock from being detected and used by TimeQuest.

Do you have a 'report clocks' option in 6.1?

There you should find all your clocks (both from outside and generated by the pll) with their frequencies.