pll input ports as unconstrained input ports with TimeQuest

Thank you very much for the quick reply.

The pll input FPGA pins are L1, L22, B12 and V12, which should be the dedicated ones for an EP2C15AF484. In the .bdf-file each input port (named clk1,...) is connected to one inclk0 of a pll block. And with 'Show Location Assignments' activated, the right FPGA pin name is shown beside the input port. Is it correct?

After read sdc file the text in the console is the following:

read_sdc

Info: Reading SDC File: 'C:/.../graphic.sdc'

Info: Deriving PLL Clocks

Info: create_generated_clock -source inst4|altpll_component|pll|inclk[0] -multiply_by 4 -name inst4|altpll_component|pll|clk[0] inst4|altpll_component|pll|clk[0]

Info: create_generated_clock -source inst4|altpll_component|pll|inclk[0] -multiply_by 4 -phase -144.00 -name inst4|altpll_component|pll|clk[2] inst4|altpll_component|pll|clk[2]

Info: create_generated_clock -source inst3|altpll_component|pll|inclk[0] -name inst3|altpll_component|pll|clk[0] inst3|altpll_component|pll|clk[0]

Info: create_generated_clock -source inst3|altpll_component|pll|inclk[0] -phase 90.00 -name inst3|altpll_component|pll|clk[2] inst3|altpll_component|pll|clk[2]

Info: create_generated_clock -source inst2|altpll_component|pll|inclk[0] -name inst2|altpll_component|pll|clk[2] inst2|altpll_component|pll|clk[2]

So this seems to work, right?

Any further ideas? Any hint is welcomed.