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Altera_Forum's avatar
Altera_Forum
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16 years ago

pll input ports as unconstrained input ports with TimeQuest

The system contains a Cyclone II FPGA, SDR SDRAM and some other components. There is one crystal oscillator connected to the four dedicated pll input FPGA pins. The configuration includes 4 plls (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Yes this should be enough to detect the unconstrained paths, you don't need to recompile.

Are you sure that your clk1,4,8,12 ports are connected to pll inputs in you design?

Do you get any warning from TimeQuest when it reads the sdc file telling that it couldn't find the port associated with the clock you create?