pll input ports as unconstrained input ports with TimeQuest

Thanks for that hint, but I tried that already and it changed nothing. At least as long as I don't have to run a full compilation again. But I read, that I only have to change the sdc file, run the 'reset design', read the sdc file again, update the timing netlist and run the 'report unconstrained paths' again. Is this correct?

I just don't understand, why the ports clk1, clk4, clk8 and clk12 are reported as unconstrained input paths. I thought, there are input paths and clk paths and since I said clk1 etc. are the targets for create_clock, it should be made clear, that those ports are clocks and no data inputs. What did I get wrong about that?

And what means the comment 'unclocked' beside the ports clk1 etc. in the list with the unconstrained input paths? Do I nead to write 'set_input_delay' for pll input ports??