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Altera_Forum's avatar
Altera_Forum
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16 years ago

pll input ports as unconstrained input ports with TimeQuest

The system contains a Cyclone II FPGA, SDR SDRAM and some other components. There is one crystal oscillator connected to the four dedicated pll input FPGA pins. The configuration includes 4 plls (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I wonder if you shouldn't write 4 create_clock lines for your 4 clock inputs, with 4 different names. They will be seen as 4 different clocks by Timequest anyway.