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Altera_Forum
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15 years ago

PLL input from non-dedicated clock pin

Hello all, I've struck with a simple problem and I'm almost nearing the wall in terms of options. I've a design in which the clock is coming from a non-dedicated clock pin (PIN_AJ16). I've...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I've added a picture to visualize the problem.

For the sake of discussion module A is a block-box and the logic cannot be altered. TimeQuest reports max frequency of Mux_Clk to be 80MHz. So, I've the following options.

1. Run Clk2 through a divider and feed to Module A.

2. Gate Clk2 before feeding Module A and Quartus will convert it to register enable. I'm assuming Quartus will merge "En2" and the new enable for frequency division. I will also have to give multi-cycle constraint in SDC, correct?

I've one more question.

How to know the individual max frequency for each of the modules? Suppose the critical path is in module B and I know I won't be using it, then theoritically I can set Clk2 to the max supported by A or C. But TimeQuest will report only for the top level clocks.

-Gopal