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Altera_Forum
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15 years ago

PLL input from non-dedicated clock pin

Hello all, I've struck with a simple problem and I'm almost nearing the wall in terms of options. I've a design in which the clock is coming from a non-dedicated clock pin (PIN_AJ16). I've...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Suppose I've to transfer data from clk domain to clk/2 then PLL can help reduce the skew on the clk/2, right?

I've added create_clock and create_generated_clock statements in the SDC file. I see sometimes wrong data being latched in clk/2 domain. I hope Quartus will automatically take care of the hold time violation due to clock skew. I will analyze it a bit further.