PLL input from non-dedicated clock pin

What device? Some of the older architectures didn't allow this type of layout.

If you're divide by 2 clock is the main clock, it may not be a big deal. The problem with gated clocks is that they have skew compared to the non-gated clocks, and so transferring data back and forth is difficult. That being said, it can be done. (What you're trying is the best option, but there are plenty of designs with gated clocks like this).

The other option is to take the divide-by-2 output and have it feed the clock enable of the register and have the clock port fed by the main clock. This disables the clock on every other cycle, and makes a divide-by-2 domain that is not skewed from the main clock domain. (In reality, everything is fed by the main clock domain). That is just as good as using a PLL, and sometimes better, since no PLL is required, no locking, no use of two clock trees, etc.