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Altera_Forum
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15 years ago

PLL inclock legal source reported as illegal

==622MHz==> FAST_PLL0 ==77MHz==>| ==622MHz==> FAST_PLL1 ==77MHz==>| CLK_CTRL ==77MHz==> ENH_PLL This is basically my setup, the select signal to the CLK_CTRL block depends on which FAST_PLL t...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Just removed option "ensure glitch-free operation" from CLK_CTRL settings seeing as the inserted registers make it a non-direct connection between PLL and CLK_CTRL. This however, generated a new error: 

Error: Port outclk of Clock Control Block "singlechannel:ch0_i|lvds_rx:lvds_rx_i|altlvds_rx:altlvds_rx_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_altclkctrl:rx_outclock_buf|clkctrl3" can't drive inclk port of Clock Control Block "clkctrl:clkctrl_i|clkctrl_altclkctrl_4ne:clkctrl_altclkctrl_4ne_component|clkctrl1"
Error: Can't merge Clock Control Blocks singlechannel:ch0_i|lvds_rx:lvds_rx_i|altlvds_rx:altlvds_rx_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_altclkctrl:rx_outclock_buf|clkctrl3 and clkctrl:clkctrl_i|clkctrl_altclkctrl_4ne:clkctrl_altclkctrl_4ne_component|clkctrl1 -- singlechannel:ch0_i|lvds_rx:lvds_rx_i|altlvds_rx:altlvds_rx_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_altclkctrl:rx_outclock_buf|clkctrl3 feeds logic that is not clkctrl:clkctrl_i|clkctrl_altclkctrl_4ne:clkctrl_altclkctrl_4ne_component|clkctrl1
This PLL chaining is driving me nuts. Is there really no way to implement my design?