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Altera_Forum
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14 years ago

PLL dedicated clock outputs

I have got the following message. Warning (15064): PLL "Std_CycloneIV:inst|cpu_pll:the_cpu_pll|cpu_pll_altpll_6nm2:sd1|pll7" output port clk[2] feeds output pin "sram_clk~output" via non-dedic...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hello bcao,

i know this warning.

In your device you have 4 PLL's.

One in every edge of your device. (Look into the Chip Planner).

Every PLL has dedicated clock input pins and output pins. (Look into the Device Handbook).

If you use one dedicated pll clock output pin to your external Memory, you

must check whether the associated pll is selected by the fitter.

If not, you can use the assignment editor to make a location assignment for the used pll to correct this.

See Attachmend.

In my case, after the location correction, the warning was gone.

I hope I could help